(1) Field of the Invention
The present invention relates to integrated circuits on semiconductor substrates, and more particularly to a method of fabricating a unified contact plug structure for electrical interconnects on Static Random Access Memory (SRAM) having Thin Film Transistors (TFT).
(2) Description of the Prior Art
Both Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) circuits are used extensively in the electronics industry for storing data for digital systems, such as computers. The SRAM is much faster than the DRAM circuit. Because of its speed the SRAM is ideal for use as a cache or buffer memory to speed up the system performance, and is therefore preferred over the DRAM device. Each of the memory cells on a SRAM device is usually composed of six transistors and functions as a static latch or flip flop circuit, does not have to be refreshed like a DRAM cell. Unfortunately, the SRAM devices require more processing steps than the DRAM and is therefore less cost effective for manufacture.
A circuit schematic for a typical six-transistor CMOS SRAM cell is shown in FIG. 1. Only one of the array of many cells is shown in FIG. 1. The trend in recent years is to fabricate the CMOS SRAMs using P channel Thin Film Transistors (TFTs) for the load transistors, labeled P1 and P2 in FIG. 1 and to use N-channel FETs formed in and on the substrate as the driver transistors, labeled N1 and N2. The N-channel FETs are also used as the pass transistors, and labeled WN1 and WN2 in FIG. 1.
Briefly, the SRAM circuit functions as follows. Address row and column decoder circuits on the periphery of the SRAM chip (not shown) select a memory cell. Referring to FIG. 1, the applied gate voltage on the word line WL switch on the pass transistors WN1 and WN2. The voltage at the nodes Q1 and Q2 between the two pairs of CMOS transistor P1, N1 and P2, N2, are sensed on the bit lines BL1 and BL2 during the read cycle to determine the state of the SRAM latch. During the write cycle when the write circuit (not shown) is enabled an impressed voltage on the bit lines can switch the voltage levels on the latch and thereby can switch the state of the cell that stored the binary data representing the one's and zero's.
Typically, during the fabrication of the SRAM circuit on a semiconductor substrate several layers of patterned conductivity doped amorphous or polysilicon films are used to form parts of the N and P-channel transistors and the intralevel connections. The polysilicon layers are separated and electrically insulated from each other by dielectric layers, such as silicon oxide. These various electrically conducting polysilicon layers and portions of the substrate are then interconnected by forming contact openings in the insulating layers between the various polysilicon layers, such as by photoresist masking and etching. Typically, the conventional SRAM cell requires a large number of masking and etching steps that include the patterning of about four polysilicon layers and about five masking and etching steps to form the contact openings between the polysilicon layers and to the substrate. It is also necessary, in the conventional process, to deposit the first polysilicon layer in two steps (split polysilicon deposition) to form the pass and driver transistors, thereby further increasing the number of process steps. Therefore, there is a very strong need in the semiconductor industry to reduce the number of processing steps.
Another concern with the conventional SRAM cell is the non-ohmic stacked contacts that are form in the contact openings, and occurs at interfaces between polysilicon layers having different types of conductive dopants (P.sup.+ /N.sup.+). These P.sup.+ /N.sup.+ diode like junctions delay the on current (I.sub.on) during switching and degrade the performance of the SRAM cell.
Several methods have been described for improving the SRAM-Thin Film Transistor (TFT) and for forming metal plug contacts to the substrate. For example, T. Okazawa, U.S. Pat. No. 4,980,732 describes a method for making TFTs with lower off currents by off setting the drain side of the FET channel and in the prior art of the same patent there is described the use of aluminium to form an ohmic contact between the P doped drain of the P-channel TFT and source of the N-channel FET formed on the substrate. Also, methods for improving the tungsten metal plugs formed in contact openings in insulators on the substrate is described by T. Hasegawa et al, U.S. Pat. No. 5,374,591, by J. M. Cleeves et al, U.S. Pat. No. 5,366,929. However, none of the cited references address the need for reducing the process steps during manufacturing of the SRAM device.
Therefore, there is still a strong need in the semiconductor industry for methods and improved structures for reducing the number of masking levels and process steps, and thereby provide a cost effective process, while at the same time improving the circuit performance by reducing the contact resistance between the polysilicon layers, such as on SRAM circuits.